Despite the many disputes surrounding the value, definition, variability, and technology of DFM, all problems are based on chips. Of course, chip DFM is a key requirement when we start thinking about 45- and 32-nanometer designs. However, the focus on chip DFM ignores more important technical requirements: DFM for printed circuit boards.

     We all know that even if the silicon is 100% perfect, if any component of the chip-to-chip communication link (such as the package, connector, or circuit board) is damaged, the target system may still not work properly. Many package, connector, and PCB suppliers may be chased by system designers to control their processing tolerances.

     However, unless all suppliers uniformly tighten the specification, for example, a system with plus or minus 5% tolerance connectors may have a small positive or negative 10% tolerance on the PCB. In order to optimize the system design, designers need to study the causality of each component. So far, we don't have DFM tools to deal with such design issues.

      During the pre-layout design phase, high-speed systems or signal integrity engineers typically only perform limited Spice simulations. To ensure that the system is working properly, you need to simulate boundary conditions that cover all process tolerances.

     For example, variations in metal line width, dielectric stack height, dielectric constant, and loss tangent within the PCB can all affect the impedance and attenuation. However, only engineers from larger companies may have the resources to customize their own scripts to perform thousands of simulations before processing the results. Even so, there is still no well-defined standard for which variable to scan.

     The most obvious lack is the boundary model of the package and connector. For high-speed designs, these models can only be precisely defined by frequency-dependent S-parameters. However, few suppliers offer good S-parameter models, let alone boundary models in a wide range of frequencies.

In the post-layout verification phase, accurate PCB extraction and simulation are required to calculate detailed corners and bends. However, almost no tools are available.

     Obviously, a common PCB design and verification method is needed. So what do we need?

     Let us focus on two major areas. For pre-layout designs, for example, it is best to have a GUI-driven wiring diagram input editor that allows designers to easily enter changes to each component, simulate and process the results, and report on the generation and impact of each variable.

For the post-layout verification, the DFM tool needs to be able to automatically adjust the layout to cover the boundary conditions, use a fast full-wave extractor to extract the parasitic parameters, and simulate the I/O transistor boundary model in the circuit simulation.

     Only when the designers take into account the difference in workmanship in design and verification can they say that manufacturability is designed. Only when the tool supplier realizes that the chip is only part of the subsystem, such as the PCB, can DFM finally be truly relevant to the customer who develops the end product.