With the increasing frequency of device operation, signal integrity issues faced by high-speed PCB designs have become a bottleneck in traditional designs, and engineers are faced with increasing challenges in designing complete solutions. Although related high-speed simulation tools and interconnection tools can help designers solve some of the challenges, high-speed PCB design also requires more experience and in-depth exchanges between the industry.

   The following are some of the issues that are of great concern.

   The effect of wiring topology on signal integrity

   Signal integrity issues can arise when signals travel along transmission lines on high-speed PCB boards. STMicroelectronics's Tong Yang asked: For a group of buses (addresses, data, commands) to drive up to four or five devices (FLASH, SDRAM, etc.), when the PCB is wired, the bus arrives at each device in turn. Connected to the SDRAM, to the FLASH ... ... or the bus is star-shaped distribution, that is separated from somewhere, connected to each device. Which of the two methods is better in terms of signal integrity?

   In this regard, Li Baolong pointed out that the effect of the wiring topology on signal integrity is mainly reflected in the fact that the arrival times of the signals on each node are inconsistent, and the time at which the reflected signal also reaches a certain node is inconsistent, thus deteriorating the signal quality. In general, the star topology can achieve better signal quality by controlling the same length of several branches so that signal transmission and reflection delays are consistent. In the use of topology, we must consider the signal topology node conditions, the actual working principle and wiring difficulty. Different Buffers have inconsistent effects on the reflection of signals. Therefore, the star topology does not solve the above problem that the data address bus is connected to the FLASH and SDRAM, and the quality of the signal cannot be ensured. On the other hand, high-speed signals are generally Communication between DSP and SDRAM, FLASH loading rate is not high, so in the high-speed simulation as long as the actual high-speed signal to ensure effective operation of the node at the waveform, and do not have to pay attention to the waveform at FLASH; star topology compared to the topology of the daisy chain It is difficult to route wiring, especially when a large number of data address signals use a star topology.

   Pad's impact on high speed signals

   In the PCB, a via is mainly composed of two parts from the design point of view: the middle hole and the pad around the hole. An engineer named furonm consulted guests about the impact of the guest pad on high-speed signals. In this regard, Li Baolong said: Pads have an impact on high-speed signals, which affect the device-like package's impact on the device. After detailed analysis, the signal comes out of the IC and passes through bonding wires, pins, package housings, pads, and solder to reach the transmission line. All the joints in the process will affect the signal quality. However, in actual analysis, it is difficult to give the specific parameters of the pad, solder, and pin. So generally they are summarized with the parameters of the package in the IBIS model, of course, such analysis can be received at a lower frequency, but more accurate simulation of higher-frequency signals is not accurate enough. The current trend is to describe Buffer characteristics using IBIS's V-I and V-T curves and describe the package parameters using the SPICE model.

  How to suppress electromagnetic interference

   PCB is the source of electromagnetic interference (EMI), so the PCB design is directly related to the electromagnetic compatibility (EMC) of electronic products. If you attach importance to EMC/EMI in high-speed PCB design, it will help shorten the product development cycle and accelerate time-to-market. Therefore, many engineers are very concerned about the issue of suppressing electromagnetic interference in this forum. For example, Shu Jian of Wuxi Xiangxiang Medical Imaging Co., Ltd. stated that the harmonics of the clock signal were found to be excessively high in the EMC test. Is it necessary to do special processing on the power pin of the IC that uses the clock signal? Decoupling capacitors are connected to the power pins. In the PCB design, there are still some aspects that need attention to suppress electromagnetic radiation. In this regard, Li Baolong pointed out that EMC's three elements are radiation sources, transmission routes and victims. The route of transmission is divided into spatial radiation propagation and cable conduction. So to suppress harmonics, first look at the way it spreads. Power supply decoupling is the solution to conduction propagation. In addition, necessary matching and shielding are also needed.

   When responding to the questions of the users of the network, Li Baolong pointed out that filtering is a good way to solve EMC's radiation through the conduction path. In addition, it can also consider the sources of interference and the victims. For interference sources, try using an oscilloscope to check if the signal's rising edge is too fast, there is a reflection or overshoot, undershoot, or ringing. If so, consider matching; try to avoid the 50% duty cycle signal because the signal is not even Subharmonics, more high frequency components. In terms of the victim’s body, measures such as land parcels can be considered.

  Whether the RF wiring is via or bent

   In this forum, there are not many netizens asking questions about high-speed analog circuit design. For example, a user of Jingheng Electronics asked: In a high-speed PCB, it is also possible to reduce the large return path. However, some people say that they would rather not bend if they want to bend. How should they choose?

   In this regard, Li Baolong pointed out that the analysis of the RF circuit's return path is not the same as the signal return in high-speed digital circuits. The two have in common, are distributed parameter circuits, are the characteristics of the Maxwell equation calculation circuit. However, the RF circuit is an analog circuit. There are voltages V=V(t) and I=I(t) in the circuit that need to be controlled. The digital circuit only pays attention to the change of the signal voltage V=V(t). Therefore, in RF wiring, in addition to considering signal reflow, it is also necessary to consider the influence of the wiring on the current. That is, the bent wiring and vias have no influence on the signal current. In addition, most RF boards are single-sided or double-sided PCBs, and do not have a complete planar layer. The return path is distributed around the signal and on the power supply. The simulation needs to use 3D field extraction tools for analysis. The via reflow requires a specific analysis; high-speed digital circuit analysis generally only deals with a multi-layer PCB with a complete planar layer. Using 2D field extraction analysis, only the signal backflow in adjacent planes is considered. The vias only serve as a lumped parameter RLC. deal with.